#MAXIM INTEGRATED is #Hiring for PHYSICAL DESIGN #PD #Bangalore

MAXIM INTEGRATED is Hiring for PHYSICAL DESIGN Engineers. Location: Bangalore. Experience: 3+ years Interested candidates kindly drop your updated CV to supreeth.ms@maximintegrated.com

Tessolve Semiconductors (a venture of Hero Electronix ) Hiring VLSI Engineer for Multiple Location. Intrested folks can reach out me

Physical Design Engineer | Invecas Technologies India Ltd

Physical Design Engineer

Hyderabad, Noida

Job Description:
Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning
Work alongside RTL/Synthesis/DFT teams to define design partitions and create floorplan as per the design data flow
Work closely with library, technology and Analog IP teams for physical design requirements
Work closely with CAD teams and involve in methodology development and improvement
Own SoC/partition physical design activities while managing a team of 4-5 engineers

Desired Skills and Experience:
Hands-on experience with Implementation (PNR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)
Tech. / M. Tech. with 4 -7 years of experience in Physical Design
The candidate should be able to work with and lead a team of engineers on all aspects of Physical Design tasks on a SOC design
Should have handled Netlist to GDS II implementation at Chip/partition level for at least 2-3 designs
Hands-on expertise with technology nodes like 28nm, 16nm and below
Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly with ICCII & Calibre
Excellent understanding of design partitioning & budgeting along with hands-on experience in Chip/partition floor planning, placement optimizations, Clock planning and routing.
Good understanding of low power implementation techniques and static low power checks
IO ring design and bump planning is a plus
Being proficient in TCL, Perl scripting is a plus

Job Features
Job Category Physical Design
Job Title Physical Design Engineer
Experience 4 -7 years
Location Of Work Hyderabad

Hiring Physical Designers (Min 3+yrs exp) for Bangalore.

Hiring Physical Designers (Min 3+yrs exp) for Bangalore. Experience: 3-8yrs INTERVIEWS WILL BE TELEPHONIC/SKYPE. If interested, please share resume to jobs@chipsolconsultant.com

World leaders in storage domain is looking for Physical Design Engineers - Bangalore

Experience: 4-10 years Location: Bangalore Product based company/ Premier college Interested candidates can DM or share profile to payal.verma@spectrumconsultants.com

Hiring PD Engineers for Noida and Bangalore | BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication)

Exp: 2-5 years Education BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) Core Competencies Knowledge of PD Flow from netlist to GDS (Floorplanning, Synthesis, Power Planning, Placement & Optimization, CTS, Routing, ECO steps, Timing/SI) Good idea about OCV/MMMC and multi-power designs (Level shifters, Isolation cells etc) Should have worked extensively on XTalk/SI/EM Knowledge of CTS, Clock tree methodology Tool-specific knowledge ICC, Innovus, primetime, DC, Genus depending on the background Knowledge of DRC/LVS, IR Drop, Formal Verification, and Synthesis. The job would require complete ownership from netlist to GDS for blocks. The physical design of Hard Macros/Partitions. Gate-level-Netlist to GDS, technologies varying from 28nm to 7nm. Should be good in TCL and PERL. Interested candidates can send their resume to hr@tecquire.in

Mirafra is hiring for below skill sets with 3+ yrs of experience for Bangalore & Hyderabad.

RTL Design Verification FPGA Design/RTL Design FPGA Emulation DFT Physical Design with Innovus If interested please share your profile @ lakshmikrishnappa@mirafra.com

Greetings from Mirafra!!!

We are currently having openings for STA, Physical Verification, DFT with 3+ Years of experience. Interested candidates cam share your updated CV to mroopa@mirafra.com
Regards Roopa M

Physical Design Engineer, Senior Engineer | Einfochips Ltd

Technical Skill [Required] 
 3-6 Yrs of experience in doing hands on physical design for complete flow of Netlist to GDSII.
Preferred Tool experience on Synopsys ICC or SoC Encounter; working on one of them for last 2 years.
Strong fundamentals on Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity on 65nm, 45nm, 28nm, 16nm geometry.
Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team player
Overall he/she need to ensure successful delivery of his block(s) to customers

Soft Skills [Required] 
This job involves good written and verbal skills.
Highly motivated technical person with problem solving attitude.
Good team player

Job Location:
Ahmedabad, Pune

Desired Candidate Profile
Please refer to the Job description above

Education-
UG:B.Tech/B.E. - Any Specialization, Electronics/Telecommunication
PG:M.Tech - Any Specialization, Electronics/Telecommunication
Doctorate:Ph.D - Advertising/Mass Communication, Electronics/Telecommunication

Company Profile
eInfochips Limited
eInfochips, an Arrow company, is a leading global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. The company’s service offerings include digital transformation and connected IoT solutions across various cloud platforms, including AWS and Azure.

Recruiter Name:Flemy John

Contact Company:eInfochips Limited

Telephone:+918980648353

Website:https://www.einfochips.com

We are looking for, Physical Design Engineer find below JD FYR.

. Should have worked on the entire PD Flow from netlist to GDS . (Floor planning, Power Planning, Placement & Optimization, CTS, Routing, . ECO steps, Timing/SI) . Should have very good idea about OCV/MM/MC and multi power designs . (Level shifters, Isolation cells etc) . Should have worked extensively on XTalk/SI/EM . Should be familiar with DSM topics like OPC/CMP etc for 65nm and lower . Technologies . Should be very strong on CTS constraints and skew fixing  Tool specific knowledge: Talus, ICC, SOC, depending on the background . Good understanding of library preparation in any environment (Synopsys, . Magma or Cadence) . Knowledge of DRC/LVS, IR Drop, Formal Verification and Synthesis an . added advantage . Job would require complete ownership from netlist to GDS for blocks. . Should have done similar job well in the past . Should have worked on 65nm and lower technologies. Core Requirements:- • Location: - Bangalore. • Experience: - 2+Years • Salary: - Open For Discussion • Notice Period: immediate/30 Days. If you interested share me your updated resume : akarsh@semicontechs.com

Tessolve Hiring for Multiple openings @ Bangalore

We have multiple requirements for engineers with 2+ Yrs experience in the following domains - ASIC Verification,
Physical Design,
Physical Verification,
Design for Test (DFT),
Analog Circuit Design and Analog Layout Design.
Location : Bangalore 

Interested candidates kindly share your resume to vlsi.hr@tessolve.com

Greetings from SiValley Technologies!!!

We are hiring for below requirements:

1. Physical Design Engineers  - 2 to 9yrs
2. Analog Layout Engineers - 2 to 9yrs
3. RTL Verification Engineers - 3 to 9yrs
4. Std Cell Layout Engineers - 2 to 8yrs
5. Std Cell Characterization - 2 to 8yrs

Interested candidates kindly share resumes to av@sivalleytech.com

Greetings from Mirafra Technologies!!!

Location :  Bangalore / Hyderabad

If interested please share your updated resumes at princekumar@mirafra.com

PHYSICAL DESIGN Engineers- 2 to 12years.

Regards

Prince Kumar

Greetings from Technovest..!

Critical hiring for a Leading US_based MNC for Bangalore, Chennai, Noida

1. DFT 4 - 8 Yrs

2. ASIC Prototyping in FPGA 3+ Yrs

3. Silicon Validation - 3+ Yrs

4. Synthesis/STA - 3+ Yrs

5. Physical Design PD - 4+ Yrs

6. FPGA/RTL Design - 4+ Yrs

Please do share your profile in you're interested reach@technovest.in

Further details please contact +918296774732

Karmic Design has excellent opportunities @ Bangalore, Manipal and Singapore

Hi,

           Karmic Design has excellent opportunities as below, open for Talents to work for cutting edge technologies.

i.              Analog Layout Design Engineers (Exp.: 3+ years)

ii.             Analog Verification Engineers (Exp.: 5+ years)

iii.            ASIC Layout Engineers (Exp.: 3+ years)

iv.           Physical Design Engineers (Exp.: 4+ years)

Location: Dallas, Bangalore, Singapore & Manipal.

Interested can write to hr@karmic.co.in

Insilico hiring for Physical Design Engineer

Happy new year all with New excited opportunities with Product Based companies

Hi All,

Interested folks can share their profile at sarishti@techsysglobal.com
for more details or detailed JOB DESCRIPTION can be provide on interest.

1. Verification IP Product Engineer ( Work Location : Noida , Experience : 2-5 yrs)

2. QRC Product Validation Engineer ( Work Location : Noida , Experience : 4-7 yrs)

3. PCB Support Application Engineer ( Work Location : Noida , Experience: 8-12 yrs)

4. Verification IP Developer ( Work Location : Noida , Experience : 3-7 yrs)

5. Acceleration IP Developer ( Work Location : Noida , Experience : 4-8 yrs)

6. Formal Verification Product Validation Engineer ( Work Location : Noida , Experience : 3-7 yrs)

7. Verification Support Application Engineer ( Work Location : Noida , Experience : 5-12 yrs)

8. Analog Design Engineer ( Work Location : Bangalore , Experience : 5-15 yrs)

9. Physical Design Engineer (Work location: Bangalore, Experience: 6+ yrs)

10. Analog layout Engineer (Work location: Bangalore, Experience: 8-12 yrs)

Greetings from First Pass Semiconductors!!!

We are recruiting now for the Domains:
Physical Design Engineers / Analog Layout / Verification Engineers.
Locations – Hyderabad & Bengaluru.
Experience - 2 to 15 years
Interested people can share your resume at:
murali.jagarlamudi@firstpass-semi.com

Looking for job change?. Then, Look at this !!!

Excellent & Immediate Openings for Sr./Lead Physical Design Engineers

 Skills :
-Knowledge of full RTL to GDSII flow ( Synthesis, STA, Floorplan, CTS, PnR, DRC/LVS, SI, IR drop )
-Hands- on experience with synopsys and Cadence PnR tools, Floorplaning, IR Drop and Physical
verification-Should have good understanding of verilog/VHDL
-Exposure to low power techniques
-Knowledge of tcl and perl scripting is a must

Location : Bangalore
Experience : 3 to 10 Years
Interested share resume to gunjan@incise.in