Blueberry Urgent Hiring #FPGA #DV #Bangalore

Blueberry Urgent Hiring! - FPGA Lead Engineer - Design Verification Engineer Experience : 4-9 Years Location : Bangalore Immediate joiners preferred. If interested, Kindly share CV to natasha@blueberrysem.com

Cerium systems is hiring!!

Cerium systems is hiring!! Skill: Design Verification Experience: 4 to 15 yrs Location: Bangalore/Vizag/Hyderabad Skill: FPGA Design Experience: 3 to 10 yrs Location: Bangalore/Vizag/Hyderabad Interested candidates kindly share your updated profile to: ayesha.pyarejan@cerium-systems.com

XILINX,Hyderabad is looking for a FPGA Design Experts with 10+Yrs of Exp.

JD: Looking for Sr design engineer with more than 10-15 years of experience of FPGA IP development and in depth knowledge of cache coherent based designs. Candidate will be responsible for architect custom cache coherent IP, design and develop FPGA based High Performance system coherent applications Excellent communication skills for working remotely with global team Knowledge of VHDL, Verilog, System Verilog (Preferred VHDL) Candidate should be able to work with verification in description and review of test cases Expertise on cache coherency protocol Knowledge of Industry standard protocols like PCIe is a big plus Very good FPGA debugging skills Understand Xilinx FPGA flow, Vivado, timing closure and validation on FPGA platforms is big plus Working knowledge of Xilinx tools and creating Vivado IPI designs. Interested candidates can reachout to shalini.recharla@xilinx.com

Greetings from Cerium Systems!!!

Greetings from Cerium Systems!!! We are hiring below skills: Design Verification - 3.5 yrs to 12 yrs FPGA Design - 3 yrs to 10 yrs DFT - 3 yrs to 12 yrs Location: Bangalore/Vizag/Hyderabad Interested Candidates kindly share your updated profile to: ayesha.pyarejan@cerium-systems.com

We are hiring for FPGA Design, Firmware Design/Testing, Embedded Design & GUI Engineer.

Greetings from Frenus Tech Pvt Ltd, Bangalore...!!!

We are hiring for FPGA Design, Firmware Design/Testing, Embedded Design & GUI Engineer. PFB the details.

=>FPGA Design: Verilog - Exp: 8-10 Years.

Familiarity with Intel Altera FPGA platforms.

Familiarity with Xilinx Zinq FPGA platforms.

Looking for someone who could join asap.

=>Firmware Engineer: C, C++. Exp: 4-8 years.

Experience with device drivers and embedded programming.

Familiarity with Xilinx Vivado toolchain and Zynq platforms.

Familiarity with Intel Quartus Prime toolchain and Altera FPGA platforms.

=>Test Engineer: Python, Jenkins. - Exp: 4-8 years.

Experience in testing embedded platforms.

Familiarity in handling boards and using the oscilloscope.

=>Embedded S/W experts. 4-10 Years

C Linux kernel internals Device driver development,

=>GUI Engineer: C, WPF - Exp: 4-8 years.

Interested, please Email/WhatsApp CV.

Email: careers@frenustech.com

Whatsapp: +91 9591577342.

Warm Regards,

www.frenustech.com

Here are some more requirements for our long term projects in Sweden /Finland

A] Embedded Engineer having either of below skills-

1. Firmware developer L1/ Phy layer-Modem development

2. Firmware developer L2/ L3 Layer

3. System Integration and Validation Engineer


B] C++ Developer-Payment Gateways


C] VLSI Engineer- Front End having either of below skills-

1. ASIC Verification Engineer- IP/ SOC

2. ASIC/ FPGA/ SOC Design- STA/ Synthesis


Interesting?

Send us your resume/ query to neha.kukde@swediumglobal.com  or sireesha.erla@swediumglobal.com or inbox us for more details.

Greetings from Technovest..!

Critical hiring for a Leading US_based MNC for Bangalore, Chennai, Noida

1. DFT 4 - 8 Yrs

2. ASIC Prototyping in FPGA 3+ Yrs

3. Silicon Validation - 3+ Yrs

4. Synthesis/STA - 3+ Yrs

5. Physical Design PD - 4+ Yrs

6. FPGA/RTL Design - 4+ Yrs

Please do share your profile in you're interested reach@technovest.in

Further details please contact +918296774732

New Year Openings for Semiconductor Domain

1.Physical Design 2.RTL Design 3.Circuit Design 4.FPGA Design 5.AMS Design 6.Digital Design 7.DFT 8.Pre and Post Silicon Validation 9.Soc/IP/AMS Verification 10.Design Verification 11.Software Validation 12.Game Design 3D 13.Modem Application 14.RF Verification 15.DSP Design Experience Level :3+year Anybody interested can share profile to raju.prasad@collabera.com

Imagination Technologies Looking for RTL Engineer

(Exp in VHDL, Verilog , RTL , FPGA , Matlab ,DSP,Synthesis ) 4 to 7 Years

Hyderabad Location .

Contact : Srinivas.kota@imgtec.com

Exciting JOB Opportunities For Design & Verification Engineers in Synapse Design @ Bangalore

JOB LOCATION: -- BANGALORE

JOB DESCRIPTIONS: --

1.) Design Verification:-- IP or SoC (UVM based)
Experience :- 3 to 10 Years
UVM and System Verilog is must. 
Must have developed UVM based environment from scratch. 
Shall have worked on SoC level verification or IP level Verification. 
Knowledge of protocols such as AXI, AHP, I2C, SPI, DDR etc.

2.) Design Verification:-- 'C' based test cases
Experience :- 3 to 10 Years
Shall have worked on full chip level SoC verification with real processor. 
Test cases are in C and environment is either UVM/ System Verilog / Verilog.
Training center or bench projects will not be considered. 

3.) Design Verification:-- PCIe/Ethernet>1G/ USB3.0
Experience :- 4 to 10 Years
UVM and System Verilog is must. 
Must have developed UVM based environment from scratch. 
Shall have worked on PHY verification of PCIe Gen-2 or Gen-3. Ethernet 1G/10G/40G/100G and USB 3.0 can also be considered.

4.) Design Verification: -- ARM CPU
Experience: - 5 to 7 Years
Familiar with ARM CPU architecture.
Must be familiar with AMBA protocols (ACE, AXI, AHB, APB).
Strong in assembly C, system Verilog, UVM back ground.
Ability to trace, debug and root cause failures in the RTL code.
o Must be familiar with waveform debug using tools like Verdi.
o Motivated to do deep dive debug, using waveforms and logs.
Familiar with Gate Level simulations.
o Hands on experience with gate level simulations with and without timing.
Hands-on with post-silicon debug is preferable.

5.) Design:-- RTL
Experience : - 3 to 10 Years
Relevant SoC integration OR IP design experience. 
Experience for developing Micro architecture from specifications and take it up to RTL coding and synthesis. 
Experience on ARM processor based SoC Integration design will be advantage.

6.) AMS Verification
Experience: - 3 to 10 Years
Experience on 14nm/10nm/7nm much.(preferably TSMC).
Should have worked on blocks like PLL, LDO, VCO, Opamps etc.. Pcie / Serdes blocks.
Expertise with Cadence virtuoso XL for editing and Mentor graphics caliber for Verification.
Senior Engineer should have experience in IP integration.

7.) Design: -- FPGA

Experience: - 5 to 10 Years

Should have Digital design experience with FPGA background.
Strong digital design fundamentals.
Knowledge of Industry Standard Interfaces (SPI, I2C, etc) is preferable.
Experience in porting processor based designs to FPGA is a plus.
Designing digital blocks in Mixed Signal chip.
FPGA Validation of digital design (RTL + Firmware).
Experience with Xilinx Zync board is plus. 
Knowledge of modelling the peripheral / drivers / models to make the complete System setup for testing the SoC on FPGA.

Email Id : amithotkar@synapse-da.com