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Showing posts with label 2-12 Years. Show all posts
Showing posts with label 2-12 Years. Show all posts
Sunday, 16 September 2018
Tuesday, 16 January 2018
Greetings from Cerium Systems !!!
Hi Everyone,
Currently we are recruiting now for the Domains:
PD Engineers / Analog Design & Analog Layout / Verification Engineers/ DFT & STA Engineers.
Locations – Bengaluru
Experience - 2 to 12+ years
Interested people can share your resume at:
swetha.kn@cerium-systems.com
Monday, 15 January 2018
We are having openings on below requirements!!!
1)RTL Design (2-12 yrs)
2)DFT (2-12 yrs)
3)STA Synthesis (2-10 yrs)
4)Verification (2-12 yrs)
5)Physical Design (2-12 yrs)
6) Analog Layout (2-12 yrs)
Interested may drop resumes to anushikakoul@mirafra.com
or can call 9111683788.
Labels:
2-12 Years,
Analog Design,
DFT,
Hyderabad,
PD,
RTL Design,
STA Synthesis,
Verification
Wednesday, 10 January 2018
Monday, 8 January 2018
We are having openings on below requirements!!!
1)RTL Design
(2-12 yrs)
2)DFT
(2-12 yrs)
3)STA Synthesis
(2-10 yrs)
4)Verification
(2-12 yrs)
5)Physical Design
(2-12 yrs)
6) Analog Layout
(2-12 yrs)
Interested may drop resumes to anushikakoul@mirafra.com
or can call 9111683788.
Saturday, 6 January 2018
Greetings from Mirafra Technologies!!!
Location : Bangalore / Hyderabad
If interested please share your updated resumes at princekumar@mirafra.com
PHYSICAL DESIGN Engineers- 2 to 12years.
Regards
Prince Kumar
Friday, 5 January 2018
Truechip Solutions is hiring for the following positions:
1) Design
Engineers with 1+ years of experience for Noida location.
2) DFT
Engineers with 2 to 6+ years of experience for Bangalore & Noida location.
3) IP(AXI,
DDR, PHY) Engineers with 3 to 8+ years of experience for Bangalore location.
4) SoC
Engineers with 3+ years of experience for Bangalore & Noida Location.
5) IP
Engineers with 1+ years of experience for Noida location.
6)
Verification Engineers with 3 to 7+ years of experience for Pune location.
To know
complete JD pls follow the link https://lnkd.in/fB7hAT3
If
interested, pls share your CV at seema.kharayat@truechip.in or careers@truechip.net
Labels:
2-12 Years,
AXI,
DDR,
Design Engineer,
DFT,
IP,
PHY,
SoC,
Verification Engineers
Opportunities Available @ Singapore
Please Share CV/References at monika.r@e-solutionsinc.com
1. Middle Ware Admin
Experience- 3-10 years
Contract- 1 Year
Visa- Singapore Citizens/PR/EP/DP
Location- Changi, Singapore
Experience in Middlware Administration, Websphere/Jboss with MQ is mandate
2. L3 Developer and Suport- Java (Full stack)
Experience- 2-9 years
Contract- 1 Year
Visa- Singapore Citizens/PR/EP/DP
Location- Changi, Singapore
Experience is mandate in full stack development, Angular JS/backbone JS, L3 Support, Java development, MVC architecture, Spring, hibernate
3. Developer Role
Experience- 2-7 years
Contract- 1 Year
Visa- Singapore Citizens/PR
Experience in
(1)ReactJS/React/JavaScript
(2) Java
(3) HTML
4. Developer Role
Experience- 3-7 years
Contract- 1 Year
Visa- Singapore Citizens/PR
Experience in
- 2-5 years of experience in the following:
- C#, Windows Communication Foundation (WCF), .Net, SQL, Oracle PL/SQL, MSSQL.
- BizTalk development (orchestration, map, schema, pipeline, business rule engine, etc) deploying applications into the BizTalk Server environment
Labels:
2-12 Years,
Changi,
HTML,
Javascript,
L3 Developer,
Middle Ware Admin,
MVC,
React,
Singapore
Hurry up!!!
We are
having openings on below requirements!!!
1)RTL Design (2-12 yrs)
2)DFT (2-12 yrs)
3)STA Synthesis (2-10 yrs)
4)Verification (2-12 yrs)
5)Physical Design
(2-12 yrs)
6) Analog Layout (2-12 yrs)
Interested may drop resumes to
princekumar@mirafra.com
or can call 9206268748
Thursday, 4 January 2018
Physical Design | DFT | AMS | Verification Engineer Openings @ Bangalore and Hyderabad
We are hiring for Physical design ,DFT and AMS (Analog Mixed Signal ) Verification Engineers .
Location : Hyderabad & Bangalore.
Experience : 2 to 12 Years.
Interested can share their updated CVs atanushikakoul@mirafra.com
Thursday, 28 December 2017
Cyient is hiring for Physical design ,DFT and AMS (Analog Mixed Signal ) Verification Engineers .
Location : Hyderabad,Pune & Bangalore.
Experience : 2 to 12 Years.
Interested can share their updated CV's to Sudhir.kakinada@cyient.com.
Thursday, 14 December 2017
Tuesday, 12 December 2017
Mirafra is Hiring RTL Design Engineers!!!
Exp: 2-12 Yrs
Interested may drop resumes to santoshbaradi@mirafra.com
Location : Bangalore,Hyderabad.
Monday, 11 December 2017
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