Physical Design Engineer | Invecas Technologies India Ltd

Physical Design Engineer

Hyderabad, Noida

Job Description:
Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning
Work alongside RTL/Synthesis/DFT teams to define design partitions and create floorplan as per the design data flow
Work closely with library, technology and Analog IP teams for physical design requirements
Work closely with CAD teams and involve in methodology development and improvement
Own SoC/partition physical design activities while managing a team of 4-5 engineers

Desired Skills and Experience:
Hands-on experience with Implementation (PNR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)
Tech. / M. Tech. with 4 -7 years of experience in Physical Design
The candidate should be able to work with and lead a team of engineers on all aspects of Physical Design tasks on a SOC design
Should have handled Netlist to GDS II implementation at Chip/partition level for at least 2-3 designs
Hands-on expertise with technology nodes like 28nm, 16nm and below
Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly with ICCII & Calibre
Excellent understanding of design partitioning & budgeting along with hands-on experience in Chip/partition floor planning, placement optimizations, Clock planning and routing.
Good understanding of low power implementation techniques and static low power checks
IO ring design and bump planning is a plus
Being proficient in TCL, Perl scripting is a plus

Job Features
Job Category Physical Design
Job Title Physical Design Engineer
Experience 4 -7 years
Location Of Work Hyderabad

IP QA – Manager | Invecas Technologies India Ltd

IP QA – Manager

Job Location:
Hyderabad, Noida

Experience  : 8-12 years

Education   : B.E. / B.tech / M.E / M.tech

Key Qualifications
Extensive experience in Analog Design/Layout/quality analysis
Experience with the design or integration of Analog IP Such as PLL, ADC, DAC, Thermal sensor etc…
Familiarity with both the SOC design flow and Analog design flow
Good understanding of Analog layout verification, digital timing and DFT requirements for SOCs
Experience with Verilog modeling and model validation
Experience with Backend views such as lef, milkyway creation and validation for Ips
Good understanding of RTL-GDSII flow in the verification context
Excellent communication skills and strong debugging skills
Strong initiative and ownership of responsibilities, productive, able to meet aggressive deadlines
Good written and verbal communication skills

Preferred Qualifications:
PDK qualification with various regression suites is a plus
Minimum working knowledge with industry sign off tools for synthesis and Implementation
Good understanding and knowledge of scripting languages such as perl and tcl

Description
You will be part of a small team responsible for Analog IP QA. Your role will be:
Verifying and releasing the deliverable requirements for Analog IP provided by external vendors.
Driving the discussions and coordinating the activities among design, QA and cad teams to ensure a clean release.
Follow up with the customers and reviewing the design and modelling methodology.
Building up and Running QA suite with various checks on incoming IP deliverables
providing support to the Invecas SOC frontend and backend design teams for integrating the Analog IP

To Apply Above Job Submit Your Resume to: https://www.invecas.com/jobs/ip-qa-manager/