ASIC Verification Openings #Bangalore

Hi All , Looking for ASIC Verification Engineers with 3 yrs of experience for Bangalore . If interested , please share your updated profile to nirmala@sevitechsystems.com

Incise Invites !!

Truechip Solutions is having openings for the Below Skills from Junior Level to Director Level

. ASIC/SOC Design : 8 + Yrs Location : Noida Role: Manager / Sr Manager Role DFT Engineers - 2-10 yrs Location : Bangalore / Noida ASIC Verification (UVM,SV): 2 to 16 Years Location : Bangalore/ Noida IP Verification : 1 - 10 Yrs Location: Noida Analog Validation : 3 to 15 Years Location : Bangalore / Hyderabad / Noida So if you are interested then please share your updated CV at seema.kharayat@truechip.in or careers@truechip.net

Greetings from i-Semiedge Solutions Pvt Ltd !!!

Greetings,                         We are hiring for some more requirements like 1. DFT Engineer  ( 0-3 yrs, Bangalore location ), 2. Analog Layout Engineer ( 2-5 yrs, Bangalore Location ) 3.Senior Member Technical Staff ( Software Engineer )  ( 4-10 yrs , Bangalore Location ) 4. RTL Design Engineer ( 2-5 yrs, Bangalore Location ) 5. Python Developer ( 5-7 yrs , Bangalore location ) 6. Verification Engineer ( 3-7 yrs , Bangalore Location ) 7. Physical Design Engineer ( 3+yrs , Bangalore Location )     Candidates who are interested share your CV to below Mention Mail ID:- jyothi.prakash@isemiedge.com

Here are some more requirements for our long term projects in Sweden /Finland

A] Embedded Engineer having either of below skills-

1. Firmware developer L1/ Phy layer-Modem development

2. Firmware developer L2/ L3 Layer

3. System Integration and Validation Engineer


B] C++ Developer-Payment Gateways


C] VLSI Engineer- Front End having either of below skills-

1. ASIC Verification Engineer- IP/ SOC

2. ASIC/ FPGA/ SOC Design- STA/ Synthesis


Interesting?

Send us your resume/ query to neha.kukde@swediumglobal.com  or sireesha.erla@swediumglobal.com or inbox us for more details.

Greetings from Cerium !!!

Tessolve Hiring for Multiple openings @ Bangalore

We have multiple requirements for engineers with 2+ Yrs experience in the following domains - ASIC Verification,
Physical Design,
Physical Verification,
Design for Test (DFT),
Analog Circuit Design and Analog Layout Design.
Location : Bangalore 

Interested candidates kindly share your resume to vlsi.hr@tessolve.com

Hiring for VLSI Engineers

ASIC/VLSI Verification & Design engineer openings in Hyderabad and Bangalore

Hi,
Immediate openings for VLSI Verification and Physical Design Engineer with Leading Company.

1. ASIC/VLSI Verification Engineer.
     -->  Strong experience in Testbench for the Block / Cluster, Testcases, Tesplans and 1 year of  experience in OVM/UVM/VMM/Test Harness.
     -->  Knowledge of industry standard protocols like Ethernet, PCIe,   MIPI,  AXI-AHB Bus etc. will be added advantage.

2. ASIC/Physical Design Engineer.
        -->  Should execute block level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Physical Design Implementation on advanced technology nodes like 28nm, 20nm for block level implementation.  Good understanding on low power concepts. Good understanding on top level physical design, partitioning and timing constraints, IR Drop.

Experience          -->  5-12 Years
Location               -->  Bangalore/Ahmedabad
Notice Period      --> Max 45 Days

Interested candidates please share your profile to sreelekha@asian-technology.com

ASIC Verification engineer openings in Bangalore and Hyderabad

Hi, 

 Kindly we are hiring ASIC verification engineers for our Bangalore and Hyderabad location. 

Exp-2+yrs Kindly share your cv at anushikakoul@mirafra.com

Are you looking for change !!!

ASIC Verification engineer openings in Bangalore

Verification Engineer people with minimum of 2 years experience .
There is an opportunity in a Service based company.If you are Interested share your CV to mention Mail ID :- jyothi.prakash@isemiedge.com

Cerium Systems | Hiring | DFT Engineer | ASIC Verification | Analog Design | Physical Design

ASIC Verification engineers openings in Bangalore | Mirafra Technologies

Hi All,

Greetings from Mirafra Technologies 

We are looking for "ASIC Verification Engineers" of 2 + years of work experience.
Interested candidates please share your updated resumes to sivajyothi@mirafra.com or reach me at 080 46249579

Cerium Systems layout design engineer openings in Bangalore

Cerium Systems is Hiring Analog Circuit Design and PD, STA , ASIC Verification , Analog Layout Design Engineers!!! Exp Req: 2-12 Years Location: Bangalore. Interested may drop resumes to swetha.kn@cerium-systems.com

L&T Technology Services hiring ASIC Verification | RTL Design| Physical Design & DFT | Jobs in Bangalore | Jobs in Pune | 3 to 8 years Exp