Hiring #FPGA Design Engineer #Bangalore #Hyderabad #Vizag

We are currently hiring for "FPGA Design(RTL)" Experts who can work on Various High-speed level protocols. Experience: 3 to 11yrs Location: Bangalore/Hyderabad/Vizag (Positon available on all locations) Send resume: chethan.devaraju@cerium-systems.com

XILINX,Hyderabad is looking for a FPGA Design Experts with 10+Yrs of Exp.

XILINX,Hyderabad is looking for a FPGA Design Experts with 10+Yrs of Exp. JD: Looking for Sr design engineer with more than 10-15 years of experience of FPGA IP development and in depth knowledge of cache coherent based designs. Candidate will be responsible for architect custom cache coherent IP, design and develop FPGA based High Performance system coherent applications Excellent communication skills for working remotely with global team Knowledge of VHDL, Verilog, System Verilog (Preferred VHDL) Candidate should be able to work with verification in description and review of test cases Expertise on cache coherency protocol Knowledge of Industry standard protocols like PCIe is a big plus Very good FPGA debugging skills Understand Xilinx FPGA flow, Vivado, timing closure and validation on FPGA platforms is big plus Working knowledge of Xilinx tools and creating Vivado IPI designs. Interested candidates can reachout to shalini.recharla@xilinx.com

#Hiring #FPGA Design Engineers #Bangalore

Immediate hiring for FPGA Design Engineers with 4+yrs of experience for Bangalore who can join within a month. If interested please share your profile @ lakshmikrishnappa@mirafra.com Regards, Lakshmi

Excellent Opportunity For FPGA Engineers : Hyderabad

Excellent Opportunity For FPGA Engineers : Experience : 3 to 5 Years Location : Hyderabad Skills : - knowledge of FPGA using Xilinx tools like Vivado and Vitis. Should be able to build and debug system using above tools. - Working experience in Video framework like Gstreamer and FFMPEG. - Good understanding on Linux driver development and OS - Good to have understanding of Video standards like MPEGx, H.26x Interested share resume to madhuri.tomar@incise.in

#XILINX,#Hyderabad is looking for a #FPGA Design Engineer

XILINX,Hyderabad is looking for a FPGA Design Engineer with cache coherent exp. Exp:10+Yrs hashtagInterested candidates can ping me@ shalini.recharla@xilinx.com

#XILINX,#Hyderabad is looking for a #FPGA Design Experts with 10+Yrs of Exp.

JD: Looking for Sr design engineer with more than 10-15 years of experience of FPGA IP development and in depth knowledge of cache coherent based designs. Candidate will be responsible for architect custom cache coherent IP, design and develop FPGA based High Performance system coherent applications Excellent communication skills for working remotely with global team Knowledge of VHDL, Verilog, System Verilog (Preferred VHDL) Candidate should be able to work with verification in description and review of test cases Expertise on cache coherency protocol Knowledge of Industry standard protocols like PCIe is a big plus Very good FPGA debugging skills Understand Xilinx FPGA flow, Vivado, timing closure and validation on FPGA platforms is big plus Working knowledge of Xilinx tools and creating Vivado IPI designs. Interested candidates can reachout to shalini.recharla@xilinx.com

XILINX,Hyderabad is looking for a FPGA Design Expert

XILINX,Hyderabad is looking for a FPGA Design Experts with 10+Yrs of Exp. JD: Looking for Sr design engineer with more than 10-15 years of experience of FPGA IP development and in depth knowledge of cache coherent based designs. Candidate will be responsible for architect custom cache coherent IP, design and develop FPGA based High Performance system coherent applications Excellent communication skills for working remotely with global team Knowledge of VHDL, Verilog, System Verilog (Preferred VHDL) Candidate should be able to work with verification in description and review of test cases Expertise on cache coherency protocol Knowledge of Industry standard protocols like PCIe is a big plus Very good FPGA debugging skills Understand Xilinx FPGA flow, Vivado, timing closure and validation on FPGA platforms is big plus Working knowledge of Xilinx tools and creating Vivado IPI designs. Interested candidates can reachout to shalini.recharla@xilinx.com

Hiring for FPGA Design Engineers #Bangalore

Immediate hiring for FPGA Design Engineers with 4+ yrs of experience for Bangalore who can join within 1 month. If interested please share your profile @ lakshmikrishnappa@mirafra.com

Cerium Systems is hiring!!

Design Verification - 3 yrs to 12 yrs
FPGA Design - 3 yrs to 12 yrs
Location: Vizag/ Hyderabad/ Bangalore

Interested ??
please share your details to :
pragathi.chighulapally@cerium-systems.com

Mirafra is hiring for below skill sets with 3+ yrs of experience for Bangalore & Hyderabad.

RTL Design Verification FPGA Design/RTL Design FPGA Emulation DFT Physical Design with Innovus If interested please share your profile @ lakshmikrishnappa@mirafra.com

Blueberry Hiring FPGA Lead Engineer!

Experience : 6+ Years Location : Bangalore Immediate joiners preferred. JD : - Hands on experience with any of the FPGA families from Xilinx, Altera(Intel), Lattice and corresponding design flow - Knowledge of FPGA architecture, IO features, IO Constraints - Thorough Knowledge of digital design fundamentals - Thorough Knowledge of Verilog - Static timing analysis, timing optimization, timing constraints, clock domain crossing - Communication protocols including I2C, SPI, UART - Experience in verification. Knowledge of System Verilog will be an advantage - Experience in FPGA bring up activities will be an advantage - Experience in debugging of RTL issues at functional level or system level will be an advantage - Working knowledge in transceiver or SerDes based protocol design. Awareness of PCI-Express protocol will be an advantage. If interested, Please share CV at natasha@blueberrysemi.com

Cerium Systems is hiring!!

Design Verification - 3 yrs to 12 yrs FPGA Design - 3 yrs to 12 yrs Location: Vizag/Hyderabad/Bangalore Interested ?? please share your details to : pragathi.chighulapally@cerium-systems.com

XILINX, Hyderabad Hiring:

B.E/M.E/M.Tech or B.S/M.S in EE/CE with at least 5 to 14 years of experience in FPGA design, validation • Strong in digital design, microarchitecture, RTL development • Knowledge of system-level architecture including buses like AXI, bridges, memory controllers such as DDR2/DDR3, and peripherals such as USB and Ethernet, High-Speed serial connectivity, etc. • Knowledge of Video domain, Connectivity such as Display port, HDMI is desired. • Proficient knowledge of VHDL and/or Verilog coding, Synthesis (XST/Vivado/Synplify) and simulation (Xilinx simulator, ModelSim, NC-Verilog, VCS etc.). • Experience with debugging of failures in FPGA Hardware system using Chipscope/Labtools or Embedded Software Applications using traditional debuggers (GDB etc.) If anyone interested to explore, please share updated resume to shalini.recharla@xilinx.com

Greetings form SiSoC!!

We are hiring ASIC Design Verification engineers(3+ Years), FPGA Design Engineers(3+ Years) who can join immediately.

Interested candidates can revert at chandrika@sisocsemi.com / hr@sisocsemi.com.

Regards

Chandrika

SION Semiconductor is hiring FPGA Design engineers with 2-6 Yrs experience with following skills

Hiring FPGA Design engineers with 2-6 Yrs experience with following skills: - Excellent RTL Coding skills using Verilog / Systemverilog - Timing closure on Xilinx / Altera FPGAs - Debugging skills using Chipscope Pro / SignalTap - Excellent in CDC and Timing analysis - Excellent Digital logic skills - Excellent communication & problem solving skills Salary - Not a constraint for right candidate. Interested candidates, please apply at - https://lnkd.in/fqaAHAH

Immediate Openings for FPGA Engineers

Skills :
*Should have good exposure to Timing concepts with hands on exposure with Timing Analysis
*Should have post layout analysis of timing and SDF exposure
*Knowledge about ASIC/FPGA design flows, various types of simulations
*Should have used liberty / lib files, Knowledgeable about timing models
*Validate the timing models of Libero SoC Flows
*Hardware Languages: Verilog, VHDL
*Good in Perl, Tcl, scripting,


Experience : 3-5 Years
Job Location: Hyderabad
Interested share resume to gunjan@incise.in