Hiring "Analog Design Engineers" with 4+yrs for "Hyderabad" Location

Interested one please drop your resume at annapurna.b@perfectvips.com
Job Description:
Experience: 4+ years of experience in Analog design
Location: Hyderabad
Key Responsibilities:
·         Architecture of the blocks or signal chain.
·         Design and simulation of the blocks like LNA/Mixers/filters/PLLs/ADC/DAC/power amplifiers
·         Owning the complete analog front-end and delivering this to SoC team.
·         Guide the layout engineer and so the post-layout verification
Preferred Qualifications
·         Proficiency in Cadence Design Environment for Analog, Mixed-Signal designs (Cadence Analog Artist, Cadence Virtuoso, SpectreRF, Assura, NCSim)
·         Prior experience in designing the following in CMOS (0.13u or lower geometries)
o    L-C VCOs, L-C DCOs, DCROs
  LO Dividers, mixers, LO buffers
  Analog PLLs (Charge pump, PFD, Loop-filter, Delta-sigma)
  Digital PLLs (TDC, Digital loop-filter)
  Polar modulators
  Oscillators
  Continuous time and/or discrete time (switched cap) analog blocks (high linearity and low-noise Filters, analog amplifier stages, voltage references, linear regulators, etc.)
  Calibration circuits for compensating process/voltage/temperature variations

Hiring Analog Layout Design Bangalore

Experience: 3 to 5 years Work location: Bangalore JD: Finfet Process (Samsung, GF Foundries) Experience in high speed SERDES Analog layouts Tools: Cadence Virtuoso XL & Calibre Interested please drop your profile to bharathi@leadsoc.com

Global Foundries VLSI internship for 2020 graduates | M.Tech Freshers | Analog Design | Memory Design | RF Design | Bengaluru

Position : Internship – 10 positions Duration: 6 months to 12 months Technologies: Analog Design, Memory Design, RF Design & SOC Work Location: Manyata Tech Park, Bengaluru, IN Required Qualifications: M.Tech Student enrolled in an accredited program on Electrical Engineering, Computer Engineering, Computer Science, Physics, or related fields. Excellent academic standing Strong written and oral communications skills Preferred Qualifications: M.Tech Student Graduating in 2020 VLSI design courses/experience Familiarity with CADENCE/SYNOPSYS design system Reach out to : rajashekar.sriramoju@globalfoundries.com

Hiring Analog Layout Engineer with experience level of 1-12 yrs

Hiring Analog Layout Engineer with experience level of 1-12 yrs (Junior to Senior level openings) PFB job details and interested candidates can share profiles to kavitha@dronait.com Analog Layout Engineer Experience: 1+ year Senior Analog Layout Engineer Experience: 3- 12 years Location: Bangalore/Kolkata/Hubli Job Description Good in programming: System Verilog, PLI/DPI interface, PERL/Shell script, C/C++, assembly language • OVM/UVM Methodology knowledge and experience • Excellent hands-on debug skills and problem-solving attitude • Must have good knowledge on the verification flows • Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC • Experience of working on Functional Verification, SoC Verification, Emulation Qualification: B.E/B.Tech or M.E/M.Tech/M.S in Electrical or Electronics

Altran is hiring for Analog/Memory layout engineers

Altran is hiring for Analog/Memory layout engineers with 2+ yrs experience for Taiwan,interested candidate can share resumes to bindulatha.donthi@altran.com

We have Immediate Job Openings for below positions for Semiconductor Domain

We have Immediate Job Openings for below positions for Semiconductor Domain. Locaion : Bangalore Location. 1.Position:Memory Design Experience: 3+ years Required Skill : EDA tools like Cadence Virtuoso, simulation tools: espcv, finsim, hspice and xa-ra. Very good debug skill, problem solving and logical reasoning skills 2.Position:Memory layout Experience: 4-10years Required Skill: Design Engineers in 7nm,other FinFET technologies,Exp on Memory Layout. Like RAM, ROM, SDRAM etc 3.Position:Senior Analog Layout Engineer Experience: 3-12years Required Skill: chip level,CMOS technologies,PLL, ADC, DAC, LDO, LNAs, Mixers,Cadence-Virtuoso/XL/GXL, 4.Position:SoC DFT Engineer Experience: 4+years Required Skill: DFT features such as Scan, MBIST, JTAG, BScan, etc 5.Position:Physical Design Experience: 3+years Required Skill: Netlist-to-GDSII,floor planning, placement, CTS, routing, crosstalk avoidance, physical verification. 6.Position:RTL Verification Experience: 2+years Required Skill: VLSI Design Flow,Frontend design/verification,APB/AHB/AXI protocol 7.Position : Analog Layout Experience: 2+years If you interested Please your CV to himabindu.b@ananthacybertech.com or contact:04030021229

Great opportunity for Analog Design Engineers who are looking to relocate to Kerela (Trivandrum) In a Leading product based company

Exp : Min 4 Yrs If you are interested lets discuss +918296774732 Or Please do share your profile hashim@technovest.in

We have Immediate Job Openings for below positions for Semiconductor Domain@Bangalore

1.Position:Memory Design Experience: 3+ years Required Skill:EDA tools like Cadence Virtuoso, simulation tools: espcv, finsim, hspice and xa-ra. Very good debug skill, problem solving and logical reasoning skills 2.Position:Memory layout Experience: 4-10years Required Skill: Design Engineers in 7nm,other FinFET technologies,Exp on Memory Layout. Like RAM, ROM, SDRAM etc 3.Position:Senior Analog Layout Engineer Experience: 3-12years Required Skill: chip level,CMOS technologies,PLL, ADC, DAC, LDO, LNAs, Mixers,Cadence-Virtuoso/XL/GXL, 4.Position:SoC DFT Engineer Experience: 4+years Required Skill: DFT features such as Scan, MBIST, JTAG, BScan, etc 5.Position:Physical Design Experience: 3+years Required Skill: Netlist-to-GDSII,floor planning, placement, CTS, routing, crosstalk avoidance, physical verification. 6.Position:RTL Verification Experience: 2+years Required Skill: VLSI Design Flow,Frontend design/verification,APB/AHB/AXI protocol, 7.Position:Analog Layout Experience: 2+years Please share your updated resume to shanthi.pilli@anantha.co.in or contact:04030021207 Thank you Shanthi

ON Semi is hiring Analog Design Engineers !!

• Responsible for analog/mixed signal block level architecture definition, design, silicon-validation involving all aspects of analog design process as required to meet datasheet/specifications, tapeout activities of simple-derivative of existing Platform. • Design verification, regression analysis across process, voltage & temperature corners, tweaking for different analog building blocks like Bandgap-reference, Voltage-Regulators, charge-pumps, LDO’s etc. as per available device models/parameters/design rules. • Work closely with Physical-design team in setting up project-specific DRC, LVS and parasitic-extraction flow, full-chip, Core & I/O floor planning adhering to ESD, EM as per the process-design-kit , reviewing design layouts and detailed drawings • Provide support and design-specific input to silicon-validation, assembly, project-management and other teams, design support on production related issues as needed. • BSEE or equivalent (MSEE a plus) with good hands-on knowledge in VLSI, semiconductor physics, Analog and CMOS circuits, circuit debug, scripting languages, simulation tools  if any one is interested, please share your resume to bhulakshmi.tankasala@onsemi.com

Greetings !!!

We are hiring for 
1)Analog Layout  2)Memory Layout  Exp : 1 year ( No to intern / Trainee) Please share your updated profile to ashwini@cambio.co.in  Thanks & Regards Ashwini

Greetings from SeviTech Systems!!!

We are hiring for the following openings for SeviTech Systems-Bangalore Interested may drop your updated resumes to dinesh.c@sevitechsystems.com Physical Design, 2 – 12 yrs. Verification Engineers, 3 – 12 yrs. DFT Engineers, 2 – 12 yrs. STA Engineers, 2 – 12 yrs. Analog layout design, 3 – 10yrs Analog circuit design, 3 –10yrs.

#LeadSoc is #hiring for #Analog Layout engineers #Bangalore

Analog Layout Design Engineers Responsibilities: Layout engineer specializing in custom deep submicron Analog layout. Interface with Design Engineers from various locations to provide feedback and implement enhancements to endure design correctness and robustness. Participate in layout reviews across various teams. Work within a team framework May involve some traveling to other design sites Requirements: The candidate must have a B.E. (Electronics) degree. M.E. / M. Tech (Electronics/Microelectronics) preferred. Experience in Custom Analog Layout and Integration is a must. The candidate must have at least 5-10 years of relevant experience. Experience with GF 14nm nodes and below. Understand issues involved in high speed analog layouts. Experience with Cadence design tools and Calibre/PVS verification tools. Good communication skills Skill scripting is a plus Interested Candidates kindly share updated Resume to #mahi@leadsoc.com

Urgent Requirements!

Analog Layout Circuit Design AMS Verification Experience-2 Yrs to 8 Yrs Location-Bangalore Interested please inbox your resumes to remyav@eximiusdesign.com

Job opportunities with DIGICOMM Semiconductors !

Hiring for below Openings !

1. Physical Design Engineer ( 3+yrs, Bangalore Location )
2. RTL Design Engineer ( 3+yrs, Bangalore Location )
3. Design & Verification ( 3+yrs, Malaysia Location )
4. Verification Engineer ( 2+yrs, Malaysia Location )
5. DFT  Engineer ( 0-5 yrs, Bangalore Location )
6. Analog Layout Design Engineer ( 2+yrs, Bangalore Location )

If anyone is interested share your CV to below mentioned Mail ID :-
jyothi.prakash@isemiedge.com

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Greetings from First Pass Semiconductors!!!

Hi Everyone, We are recruiting now for the Domains: PD Engineers / Analog Layout / Verification Engineers. Locations – Hyderabad & Bengaluru. Experience - 2 to 15 years Interested people can share your resume at: murali.jagarlamudi@firstpass-semi.com Contact :+917097049224

Greetings from Cerium Systems !!!

Hi Everyone, Currently we are recruiting now for the Domains: PD Engineers / Analog Design & Analog Layout / Verification Engineers/ DFT & STA Engineers. Locations –  Bengaluru Experience - 2 to 12+ years Interested people can share your resume at: swetha.kn@cerium-systems.com

We are hiring for Physical Design/Verification and Analog Layout Engineers.

Experience: 2 to 10yrs Location: Bangalore If interested please inbox your profile to shivaranjini@digicomm.org

Truechip Solutions is having openings for the Below Skills from Junior Level to Director Level

. ASIC/SOC Design : 8 + Yrs Location : Noida Role: Manager / Sr Manager Role DFT Engineers - 2-10 yrs Location : Bangalore / Noida ASIC Verification (UVM,SV): 2 to 16 Years Location : Bangalore/ Noida IP Verification : 1 - 10 Yrs Location: Noida Analog Validation : 3 to 15 Years Location : Bangalore / Hyderabad / Noida So if you are interested then please share your updated CV at seema.kharayat@truechip.in or careers@truechip.net

We are having openings on below requirements!!!

1)RTL Design (2-12 yrs) 2)DFT (2-12 yrs) 3)STA Synthesis (2-10 yrs) 4)Verification (2-12 yrs) 5)Physical Design (2-12 yrs) 6) Analog Layout (2-12 yrs) Interested may drop resumes to anushikakoul@mirafra.com or can call 9111683788.