Position : Internship – 10 positions
Duration: 6 months to 12 months
Technologies: Analog Design, Memory Design, RF Design & SOC
Work Location: Manyata Tech Park, Bengaluru, IN
Required Qualifications:
M.Tech Student enrolled in an accredited program on Electrical Engineering, Computer Engineering, Computer Science, Physics, or related fields.
Excellent academic standing
Strong written and oral communications skills
Preferred Qualifications:
M.Tech Student Graduating in 2020
VLSI design courses/experience
Familiarity with CADENCE/SYNOPSYS design system
Reach out to : rajashekar.sriramoju@globalfoundries.com
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Showing posts with label Memory Design. Show all posts
Showing posts with label Memory Design. Show all posts
Saturday, 29 February 2020
Saturday, 6 October 2018
Openings from InSemi Technology
Greetings From InSemi Technology !!
We Have openings for :
Analog Layout : 2+ Years
Memory Design : 2+ Years
Memory Layout : 2+ Years
Physical Design : 2+ Years
Verification : 3+ Years
DFT : 3+ Years .....
VLSI CAD : 3+ Years
If you are interested in this opportunity please share me your profile to anthosh.ajayakumar@insemitech.com
We Have openings for :
Analog Layout : 2+ Years
Memory Design : 2+ Years
Memory Layout : 2+ Years
Physical Design : 2+ Years
Verification : 3+ Years
DFT : 3+ Years .....
VLSI CAD : 3+ Years
If you are interested in this opportunity please share me your profile to anthosh.ajayakumar@insemitech.com
Friday, 2 February 2018
We have Immediate Job Openings for below positions for Semiconductor Domain
We have Immediate Job Openings for below positions for Semiconductor Domain.
Locaion : Bangalore Location.
1.Position:Memory Design
Experience: 3+ years
Required Skill : EDA tools like Cadence Virtuoso, simulation tools: espcv, finsim, hspice and xa-ra. Very good debug skill, problem solving and logical reasoning skills
2.Position:Memory layout
Experience: 4-10years
Required Skill: Design Engineers in 7nm,other FinFET technologies,Exp on Memory Layout. Like RAM, ROM, SDRAM etc
3.Position:Senior Analog Layout Engineer
Experience: 3-12years
Required Skill: chip level,CMOS technologies,PLL, ADC, DAC, LDO, LNAs, Mixers,Cadence-Virtuoso/XL/GXL,
4.Position:SoC DFT Engineer
Experience: 4+years
Required Skill: DFT features such as Scan, MBIST, JTAG, BScan, etc
5.Position:Physical Design
Experience: 3+years
Required Skill: Netlist-to-GDSII,floor planning, placement, CTS, routing, crosstalk avoidance, physical verification.
6.Position:RTL Verification
Experience: 2+years
Required Skill: VLSI Design Flow,Frontend design/verification,APB/AHB/AXI protocol
7.Position : Analog Layout
Experience: 2+years
If you interested Please your CV to himabindu.b@ananthacybertech.com or contact:04030021229
Monday, 29 January 2018
We have Immediate Job Openings for below positions for Semiconductor Domain@Bangalore
1.Position:Memory Design
Experience: 3+ years
Required Skill:EDA tools like Cadence Virtuoso, simulation tools: espcv, finsim, hspice and xa-ra. Very good debug skill, problem solving and logical reasoning skills
2.Position:Memory layout
Experience: 4-10years
Required Skill: Design Engineers in 7nm,other FinFET technologies,Exp on Memory Layout. Like RAM, ROM, SDRAM etc
3.Position:Senior Analog Layout Engineer
Experience: 3-12years
Required Skill: chip level,CMOS technologies,PLL, ADC, DAC, LDO, LNAs, Mixers,Cadence-Virtuoso/XL/GXL,
4.Position:SoC DFT Engineer
Experience: 4+years
Required Skill: DFT features such as Scan, MBIST, JTAG, BScan, etc
5.Position:Physical Design
Experience: 3+years
Required Skill: Netlist-to-GDSII,floor planning, placement, CTS, routing, crosstalk avoidance, physical verification.
6.Position:RTL Verification
Experience: 2+years
Required Skill: VLSI Design Flow,Frontend design/verification,APB/AHB/AXI protocol,
7.Position:Analog Layout
Experience: 2+years
Please share your updated resume to shanthi.pilli@anantha.co.in or contact:04030021207
Thank you
Shanthi
#Immediate openings for memory design and verification
Location Bangalore
Job type : Permanent.
Exp: 4 – 10 Years
Notice period:Immediate-30 days
JD :
Role: Design/verification of SRAM/RF/CAM custom/compiler memories in 7FF/16FF technologies.
Responsibilities:
.Logic verification with ESPCV and custom vectors, powerup/lockup simulation, Signal Integrity analysis, EM/IR analysis, stress test using lib number,
· characterization, block level design analysis, design optimization.
· Skills and experiences needed: EDA tools like Cadence Virtuoso, simulation tools: espcv, finsim, hspice and xa-ra. Very good debug skill, problem solving and logical reasoning skills.
Thank you
Navya
Email: navya.b@anantha.co.in
L +91 4030021230
Friday, 26 January 2018
Opening for Memory Design position #Bangalore
Location : Bangalore
Exp : 4-10 Years
Required Skills:
1.Drawing layouts for schematics created by Design Engineers in 7nm & other FinFET technologies
2.Experience on Memory Layout. Like RAM, ROM, SDRAM etc.
3.Good knowledge on Memory layout techniques like Area/Speed/Power optimization
4.Good knowledge on different Memory Architecture & Compilers
5.Knowledge on BIT cell, data line & Address line routing concepts
6.Effectively communicate with Design Engineers to clarify and interpret the layout requirements based on the schematics
7.Prepare layout floor-plan & review it with the Design Engineer
8.Create layouts in the Cadence Virtuoso CAD platform as per floor-plan
9.Run DRC, LVS & other verifications required by customer to ensure layout meets foundry requirements
10.Provide feedback to Design Engineers on any modifications to schematics after layouts are completed
11.Support RC-extraction, IR drop & other post-layout analysis of layouts as per Design Engineers requirements
Forward CV : sailaja.b@anantha.co.in
For More Details Contact : 040 30021207
References will be appreciable
Thursday, 25 January 2018
#Immediate openings for memory design and verification #Bangalore
Location Bangalore
Job type : Permanent.
Exp: 4 – 10 Years
Notice period:Immediate-30 days
JD :
Role: Design/verification of SRAM/RF/CAM custom/compiler memories in 7FF/16FF technologies.
Responsibilities:
.Logic verification with ESPCV and custom vectors, powerup/lockup simulation, Signal Integrity analysis, EM/IR analysis, stress test using lib number,
· characterization, block level design analysis, design optimization.
· Skills and experiences needed: EDA tools like Cadence Virtuoso, simulation tools: espcv, finsim, hspice and xa-ra. Very good debug skill, problem solving and logical reasoning skills.
Thank you
Shanthi
Email:shanthi.pilli@anantha.co.in
L +91 4030021207
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