We have Openings on Below Requirements @ Bangalore

1) RFIC Design 2-10 Years Product Company 2) RFIC , mmWave 5G 7-14 Years Product Company 3) RF Layout Design 5-12 Years Product Company 4) CPU/ARM Verificat 4-10 Years Product Company 5) ASIC IP Design 6-11 Years Product Company 6) Asic/Soc Verification 5-8 Years Service Company 7) DFT 5-9 Years Service Company 8) STA, SOC Block Level 5-8 Years Service Company With GOOD CTC + LOTS OF STOCKS Please Share your Updated CV to krishna.m@cambio.co.in

Immediate Hiring for Synthesis engineer at Wafer Space

Immediate Hiring for Synthesis engineer at Wafer Space 8+ Years of experience in ASIC Synthesis ASIC Synthesis experience - Tool Experiecne - Synopsys DC, Cadence Genus Experience in timing constraints development Should have handled full chip synthesis Experience in Low Power/UPF based designs Good at Synthesis Optimization techniques Good experience with Physical aware synthesis Good experience with pre-layout timing analysis The candidate is expected to own the full chip synthesis activity. Should be able to plan the bottom-up synthesis strategy for complete SoC, which involves multiple power and voltage domains. Anybody interested or has any references can share profile to vikas@waferspace.com.

Tessolve Hiring VLSI Engineers for Bangalore , Hyd , Chennai and Noida

Looking for ASIC/SOC verification Engineers

Looking for ASIC/SOC verification Engineers for Hyderabad location with 3 to 6 years of experience in Systemverillog and uvm please share resume to ashok.patil@estdblr.com

Hiring ASIC / SOC Design engineers | Tessolve Semiconductor Pvt Ltd (A Hero Electronix Venture)

Truechip Solutions is having openings for the Below Skills from Junior Level to Director Level

. ASIC/SOC Design : 8 + Yrs Location : Noida Role: Manager / Sr Manager Role DFT Engineers - 2-10 yrs Location : Bangalore / Noida ASIC Verification (UVM,SV): 2 to 16 Years Location : Bangalore/ Noida IP Verification : 1 - 10 Yrs Location: Noida Analog Validation : 3 to 15 Years Location : Bangalore / Hyderabad / Noida So if you are interested then please share your updated CV at seema.kharayat@truechip.in or careers@truechip.net

Looking for ASIC RTL Engineers !

Immediate Openings for ASIC RTL Engineers with 1+yrs. Strong experience in RTL Coding/Micro architecture Design - Tools: CDC/Spyglass/Linting.

Interested one's,  Share me your updated resume to deepakp@eximiusdesign.com

Very excited opportunity with leading MNC !!!

Skill: Physical Design ( 5 + year)

Location : Bangalore

Skill : RTL Design ( Asic/SOC/IP) ---4+ year

Location : Noida

Interested pls share their profile at sarishti@techsysglobal.com

detailed JD can be provided on interest.

SiSoC Hiring for below skills for our prestigious client !!!

New Year Openings for Semiconductor Domain

1.Physical Design 2.RTL Design 3.Circuit Design 4.FPGA Design 5.AMS Design 6.Digital Design 7.DFT 8.Pre and Post Silicon Validation 9.Soc/IP/AMS Verification 10.Design Verification 11.Software Validation 12.Game Design 3D 13.Modem Application 14.RF Verification 15.DSP Design Experience Level :3+year Anybody interested can share profile to raju.prasad@collabera.com

Cypress Semiconductor is hiring multiple openings @ Bangalore

Intsemi Technologies is hiring multiple openings !

ASIC Design Engineer Openings in Bangalore

ASIC RTL Design openings in Bangalore | Mindlance Technologies

Excellent Opportunities for Interns and Freshers who have worked on  ASIC RTL DESIGN with EDA tools like: Spyglass, LEC ,Lint or CDC, or has done internship on using these skill sets. Interested can send there resume to sangeetha.m0496@mindlancetech.com                                 or you can call me @ 08067821413.