Openings from InSemi Technology

Greetings From InSemi Technology !!

We Have openings for :

Analog Layout : 2+ Years
Memory Design : 2+ Years
Memory Layout : 2+ Years
Physical Design : 2+ Years
Verification : 3+ Years
DFT : 3+ Years .....
VLSI CAD : 3+ Years

If you are interested in this opportunity please share me your profile to anthosh.ajayakumar@insemitech.com

We have Immediate Job Openings for below positions for Semiconductor Domain

We have Immediate Job Openings for below positions for Semiconductor Domain. Locaion : Bangalore Location. 1.Position:Memory Design Experience: 3+ years Required Skill : EDA tools like Cadence Virtuoso, simulation tools: espcv, finsim, hspice and xa-ra. Very good debug skill, problem solving and logical reasoning skills 2.Position:Memory layout Experience: 4-10years Required Skill: Design Engineers in 7nm,other FinFET technologies,Exp on Memory Layout. Like RAM, ROM, SDRAM etc 3.Position:Senior Analog Layout Engineer Experience: 3-12years Required Skill: chip level,CMOS technologies,PLL, ADC, DAC, LDO, LNAs, Mixers,Cadence-Virtuoso/XL/GXL, 4.Position:SoC DFT Engineer Experience: 4+years Required Skill: DFT features such as Scan, MBIST, JTAG, BScan, etc 5.Position:Physical Design Experience: 3+years Required Skill: Netlist-to-GDSII,floor planning, placement, CTS, routing, crosstalk avoidance, physical verification. 6.Position:RTL Verification Experience: 2+years Required Skill: VLSI Design Flow,Frontend design/verification,APB/AHB/AXI protocol 7.Position : Analog Layout Experience: 2+years If you interested Please your CV to himabindu.b@ananthacybertech.com or contact:04030021229

We have Immediate Job Openings for below positions for Semiconductor Domain@Bangalore

1.Position:Memory Design Experience: 3+ years Required Skill:EDA tools like Cadence Virtuoso, simulation tools: espcv, finsim, hspice and xa-ra. Very good debug skill, problem solving and logical reasoning skills 2.Position:Memory layout Experience: 4-10years Required Skill: Design Engineers in 7nm,other FinFET technologies,Exp on Memory Layout. Like RAM, ROM, SDRAM etc 3.Position:Senior Analog Layout Engineer Experience: 3-12years Required Skill: chip level,CMOS technologies,PLL, ADC, DAC, LDO, LNAs, Mixers,Cadence-Virtuoso/XL/GXL, 4.Position:SoC DFT Engineer Experience: 4+years Required Skill: DFT features such as Scan, MBIST, JTAG, BScan, etc 5.Position:Physical Design Experience: 3+years Required Skill: Netlist-to-GDSII,floor planning, placement, CTS, routing, crosstalk avoidance, physical verification. 6.Position:RTL Verification Experience: 2+years Required Skill: VLSI Design Flow,Frontend design/verification,APB/AHB/AXI protocol, 7.Position:Analog Layout Experience: 2+years Please share your updated resume to shanthi.pilli@anantha.co.in or contact:04030021207 Thank you Shanthi

Immediate Opportunity_Memory layout_3yrs #Bangalore

Greetings from SiValley Technologies!!!
1. Drawing layouts for schematics created by Design Engineers in 7nm and other FinFET technologies 2. Experience on Memory Layout. Like RAM, ROM, SDRAM etc. 3. Good knowledge on Memory layout techniques like Area/Speed/Power optimization 4. Good knowledge on different Memory Architecture and Compilers 5. Knowledge on BIT cell, data line & Address line routing concepts 6. Effectively communicate with Design Engineers to clarify and interpret the layout requirements based on the schematics 7. Prepare layout floor-plan and review it with the Design Engineer 8. Create layouts in the Cadence Virtuoso CAD platform as per floor-plan 9. Run DRC, LVS and other verifications required by customer to ensure layout meets foundry requirements  Experience: 3 + years Job Location: Bengaluru. Immediate/15 days preferred. Interested candidates, please share the updated resume:- av@sivalleytech.com

Greetings !!!

We are hiring for 
1)Analog Layout  2)Memory Layout  Exp : 1 year ( No to intern / Trainee) Please share your updated profile to ashwini@cambio.co.in  Thanks & Regards Ashwini

Hiring for Noida Location !

Immediate Opening For Memory Layout Engineers

Location : Noida  Experience : 6 months to 2 years  Interested candidates share resume to madhuri.tomar@incise.in  

Immediate Hiring for the Following Skills

Analog Layout : 3+ years :Scheduled Drive in Bangalore on 13th Jan.(Sat).

Memory Layout : 2+ years : Bangalore / Hyderabad / Noida.

Std. Cell Layout : 3+ yrs. : Bangalore

Std. Cell Char/Characterisation : 3+ yrs. : Bangalore

Please reply to varada.srinivas@cambio.co.in

### Global Level _Core Semiconductor Ppportunities # Product/Service ###

1.RTL : Mid - Very Senior Level : Memory/Serdes/Phy/DMA/DSP :Blr/Hyd.
2.Verification : Mid - Senior Level : Memory/CPU/GPU/FPGA : Blr/Hyd/Noida/Ahmedabad/Sweden.
3.Logic Synthesis : Automotive/Memory chip : Blr/Hyd.
4.STA : Senior - Lead Level : Automotive/Memory chip : Blr/Hyd/Malaysia.
5.DFT : Senior Level : Memory/Serdes Chip : Hyd.
6.PD : Mid - Director Level : Automotive/Memory chip : Blr/Hyd/Noida/Malaysia.
7.Circuit/Memory- Design/Layout : Mid- Lead Level : Memory chip : Blr/Hyd/Noida.
8.CAD/PDK/Flow Design/IPQA : Mid - Lead Level : Memory chip : Blr/Hyd.
9.PSV/Test/Validation/ATE : Mid- Lead Level : Functional/Characterization/Subsystem/Automotive chip/Memory chip/PCIE/Serdes/Microcontroller : Blr/Hyd.
10.IoT/Embedded : Jnr- Director Level :MAC/FPGA/RF/Audio DSP/Hw/Sw/Board Level/PCB : Blr/Hyd.

More information reach to gopinath@bharatheadhunters.com. Cell:9945324381.

Altan is hiring Analog & Memory layout openings in Taiwan

Altran is hiring for TAIWAN location  for "ANALOG layout" & "Memory layout" with 2+ yrs experience,if interested please share your updated resume to bindulatha.donthi@altran.com

Analog or Memory Layout Design Engineer Openings in Canada & US

Recruiting Analog or Memory Layout Design Engineers with 3+ Yrs of relevant work exp for opportunities in Canada & US (preferred immediate hires). 

Mail profiles to shashidhar_s@sankalpsemi.com