Excellent Opportunities for the Following Skills @ Bangalore.

Excellent Opportunities for the Following Skills @ Bangalore. 1) BIOS Development : (NO to Testing & Validation) : BIOS and Firmware development in C for Server BIOS Firmware with minimum 8 TO 12 years of experience in BIOS/UEFI development (Mandatory). 2)Verification having PCIE & USB Protocols with 3+ to 8 Yrs. Please inbox your profile to varada.srinivas@cambio.co.in

#Immediate openings for memory design and verification #Bangalore

Location Bangalore Job type : Permanent. Exp: 4 – 10 Years Notice period:Immediate-30 days JD : Role: Design/verification of SRAM/RF/CAM custom/compiler memories in 7FF/16FF technologies. Responsibilities: .Logic verification with ESPCV and custom vectors, powerup/lockup simulation, Signal Integrity analysis, EM/IR analysis, stress test using lib number, · characterization, block level design analysis, design optimization. · Skills and experiences needed: EDA tools like Cadence Virtuoso, simulation tools: espcv, finsim, hspice and xa-ra. Very good debug skill, problem solving and logical reasoning skills. Thank you Shanthi Email:shanthi.pilli@anantha.co.in L +91 4030021207

Hiring for #Verification #PD #AL

Job opportunities with DIGICOMM Semiconductors !

We are having openings on below requirements!!!

1)RTL Design (2-12 yrs) 2)DFT (2-12 yrs) 3)STA Synthesis (2-10 yrs) 4)Verification (2-12 yrs) 5)Physical Design (2-12 yrs) 6) Analog Layout (2-12 yrs) Interested may drop resumes to anushikakoul@mirafra.com or can call 9111683788.

Current Opportunities @ FIRSTPASS

FIRSTPASS is hiring for Multiple Positions!

We are having openings on below requirements!!!

 

1)RTL Design          (2-12 yrs)

2)DFT                        (2-12 yrs)

3)STA Synthesis     (2-10 yrs)

4)Verification          (2-12 yrs)

5)Physical Design  (2-12 yrs)

6) Analog Layout    (2-12 yrs)

Interested may drop resumes to anushikakoul@mirafra.com

or can call 9111683788.

Walk in interview for RTL Design | FPGA | Analog Design & Layout | Verification | Physical Design | Opennings @ Bangalore

### Global Level _Core Semiconductor Ppportunities # Product/Service ###

1.RTL : Mid - Very Senior Level : Memory/Serdes/Phy/DMA/DSP :Blr/Hyd.
2.Verification : Mid - Senior Level : Memory/CPU/GPU/FPGA : Blr/Hyd/Noida/Ahmedabad/Sweden.
3.Logic Synthesis : Automotive/Memory chip : Blr/Hyd.
4.STA : Senior - Lead Level : Automotive/Memory chip : Blr/Hyd/Malaysia.
5.DFT : Senior Level : Memory/Serdes Chip : Hyd.
6.PD : Mid - Director Level : Automotive/Memory chip : Blr/Hyd/Noida/Malaysia.
7.Circuit/Memory- Design/Layout : Mid- Lead Level : Memory chip : Blr/Hyd/Noida.
8.CAD/PDK/Flow Design/IPQA : Mid - Lead Level : Memory chip : Blr/Hyd.
9.PSV/Test/Validation/ATE : Mid- Lead Level : Functional/Characterization/Subsystem/Automotive chip/Memory chip/PCIE/Serdes/Microcontroller : Blr/Hyd.
10.IoT/Embedded : Jnr- Director Level :MAC/FPGA/RF/Audio DSP/Hw/Sw/Board Level/PCB : Blr/Hyd.

More information reach to gopinath@bharatheadhunters.com. Cell:9945324381.