We are hiring for following requirements #Bangalore

#LeadSoc is #Hiring for IP or #SOCs Verification #Bangalore & #Hyderabad

Job Discription : * Min 2 years of experience * Experienced with development of UVM, OVM, VMM and System Verilog test benches and usage of simulation tools/debug environments * Strong understanding of state of the art of verification techniques including assertion and metric-driven verification * Strong understanding of different phases of ASIC and/or full custom chip development is required. * Verification experience in protocols like AMBA, DDR, PCIe, Ethernet, Processors, Graphics is a plus Interested Candidates kindly share updated Resume to #mahi@leadsoc.com

Urgent Job Openings for the Following skills

PD / DFT / STA : 2+ years @ Bangalore / Noida
DV Engineer : 2+ years @ Noida
IP/SOC VERIFICATION :: 1-6 YEARS:: NOIDA
IP/SOC VERIFICATION :: 3+ YEARS :: BANGALORE
Verification Engineers :3 + years : Pune

Please reply to varada.srinivas@cambio.co.in

Cypress Semiconductor is hiring multiple openings @ Bangalore

Greetings from RAKIYA Information Technology Solution!

Hi, Urgent Requirements :- 1.RTL/FPGA Design : - 03+ Years 2. IP/ SOC Verification : - 02+Years 3. Validation (Post Silicon / Pre Silicon) : - 02+ Years Job Location - Bangalore Let me know your interest for joining with us. If you are Interested, Share your profile to      :           urmila@rakiyaworld.com Thank you Best Regards Urmila HR and BDE

Excellent opportunity for M.Tech / M.S. Freshers (VLSI / Digital Electronics)

Excellent opportunity for M.Tech / M.S. Freshers (VLSI / Digital Electronics) 2015/16 Passed outs who are looking for SoC Verification openings.

Desired skills:
1) Excellent Digital logic design
2) Excellent Verilog programming skills
3) Excellent Problem solving skills
4) Who can join in less than 15 days

Interested candidates, please apply at - http://www.sionsemi.com/career/employment-application-freshers.html
NOTE: Candidates who already applied during last 6 months, need not apply.

Spatez hiring various openings in Trivandrum

1. Physical design engineer (2-8 yrs) 2. SOC Verification engineer (3-8 yrs) 3. Analog layout engineer (2-8 yrs) 4. LABVIEW Developer (2-8 yrs) 5.Post silicon validation(ATE/BENCH char) - (3-12yrs) 6.RF Engineer ( 4-8 yrs) 7. Standcell layout and design engineer(2-8 yrs) 8.Memory design and characterisation (1-8 yrs) Salary: Negotiable(Not a constant for a right candidate) If any one finds suitable to you then share your CV to (wearehiring@spatez.com / dany@spatez.com) so that will get back to you. Or else share with your friends who are looking for change also. Looking forward to hear from you people. Note: Sorry Freshers are not considered  Thanks & Regards., Ms. Dany Maria Davis HR Manager Spatez Group of Companies Shell | Infosys | Tata Consultancy Services