We have openings for Senior Verification Engineer
JD: Excellent knowledge in System Verilog, UVM/OVM methodology, Creating test cases, test bench, run regressions and analyze reports along with coverage. Very good debugging skills. Knowledge of Ethernet protocols and high speed transceiver interfaces. Verification, create TB/TC, debug, analyze coverage, test and run regressions and report If Interested, Please share your profile to ragavalli.pachipulusu@forayusoft.com 9063886006
JD: Excellent knowledge in System Verilog, UVM/OVM methodology, Creating test cases, test bench, run regressions and analyze reports along with coverage. Very good debugging skills. Knowledge of Ethernet protocols and high speed transceiver interfaces. Verification, create TB/TC, debug, analyze coverage, test and run regressions and report If Interested, Please share your profile to ragavalli.pachipulusu@forayusoft.com 9063886006
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