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Showing posts with label Memory Characterisation. Show all posts
Showing posts with label Memory Characterisation. Show all posts
Wednesday, 29 November 2017
Spatez hiring various openings in Trivandrum
1. Physical design engineer (2-8 yrs)
2. SOC Verification engineer (3-8 yrs)
3. Analog layout engineer (2-8 yrs)
4. LABVIEW Developer (2-8 yrs)
5.Post silicon validation(ATE/BENCH char) - (3-12yrs)
6.RF Engineer ( 4-8 yrs)
7. Standcell layout and design engineer(2-8 yrs)
8.Memory design and characterisation (1-8 yrs)
Salary: Negotiable(Not a constant for a right candidate)
If any one finds suitable to you then share your CV to (wearehiring@spatez.com / dany@spatez.com) so that will get back to you.
Or else share with your friends who are looking for change also.
Looking forward to hear from you people.
Note: Sorry Freshers are not considered
Thanks & Regards.,
Ms. Dany Maria Davis
HR Manager
Spatez Group of Companies
Shell | Infosys | Tata Consultancy Services
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