Skills :
*Should have good exposure to Timing concepts with hands on exposure with Timing Analysis
*Should have post layout analysis of timing and SDF exposure
*Knowledge about ASIC/FPGA design flows, various types of simulations
*Should have used liberty / lib files, Knowledgeable about timing models
*Validate the timing models of Libero SoC Flows
*Hardware Languages: Verilog, VHDL
*Good in Perl, Tcl, scripting,
Experience : 3-5 Years
Job Location: Hyderabad
Interested share resume to gunjan@incise.in
*Should have good exposure to Timing concepts with hands on exposure with Timing Analysis
*Should have post layout analysis of timing and SDF exposure
*Knowledge about ASIC/FPGA design flows, various types of simulations
*Should have used liberty / lib files, Knowledgeable about timing models
*Validate the timing models of Libero SoC Flows
*Hardware Languages: Verilog, VHDL
*Good in Perl, Tcl, scripting,
Experience : 3-5 Years
Job Location: Hyderabad
Interested share resume to gunjan@incise.in
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