#XILINX,#Hyderabad is looking for a #FPGA Design Experts with 10+Yrs of Exp.

JD: Looking for Sr design engineer with more than 10-15 years of experience of FPGA IP development and in depth knowledge of cache coherent based designs. Candidate will be responsible for architect custom cache coherent IP, design and develop FPGA based High Performance system coherent applications Excellent communication skills for working remotely with global team Knowledge of VHDL, Verilog, System Verilog (Preferred VHDL) Candidate should be able to work with verification in description and review of test cases Expertise on cache coherency protocol Knowledge of Industry standard protocols like PCIe is a big plus Very good FPGA debugging skills Understand Xilinx FPGA flow, Vivado, timing closure and validation on FPGA platforms is big plus Working knowledge of Xilinx tools and creating Vivado IPI designs. Interested candidates can reachout to shalini.recharla@xilinx.com