Blueberry Hiring FPGA Lead Engineer!

Experience : 6+ Years Location : Bangalore Immediate joiners preferred. JD : - Hands on experience with any of the FPGA families from Xilinx, Altera(Intel), Lattice and corresponding design flow - Knowledge of FPGA architecture, IO features, IO Constraints - Thorough Knowledge of digital design fundamentals - Thorough Knowledge of Verilog - Static timing analysis, timing optimization, timing constraints, clock domain crossing - Communication protocols including I2C, SPI, UART - Experience in verification. Knowledge of System Verilog will be an advantage - Experience in FPGA bring up activities will be an advantage - Experience in debugging of RTL issues at functional level or system level will be an advantage - Working knowledge in transceiver or SerDes based protocol design. Awareness of PCI-Express protocol will be an advantage. If interested, Please share CV at natasha@blueberrysemi.com