Hiring FPGA Design engineers with 2-6 Yrs experience with following skills:
- Excellent RTL Coding skills using Verilog / Systemverilog
- Timing closure on Xilinx / Altera FPGAs
- Debugging skills using Chipscope Pro / SignalTap
- Excellent in CDC and Timing analysis
- Excellent Digital logic skills
- Excellent communication & problem solving skills
Salary - Not a constraint for right candidate.
Interested candidates, please apply at - https://lnkd.in/fqaAHAH
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