Immediate Opportunity_Memory layout_3yrs #Bangalore

Greetings from SiValley Technologies!!!
1. Drawing layouts for schematics created by Design Engineers in 7nm and other FinFET technologies 2. Experience on Memory Layout. Like RAM, ROM, SDRAM etc. 3. Good knowledge on Memory layout techniques like Area/Speed/Power optimization 4. Good knowledge on different Memory Architecture and Compilers 5. Knowledge on BIT cell, data line & Address line routing concepts 6. Effectively communicate with Design Engineers to clarify and interpret the layout requirements based on the schematics 7. Prepare layout floor-plan and review it with the Design Engineer 8. Create layouts in the Cadence Virtuoso CAD platform as per floor-plan 9. Run DRC, LVS and other verifications required by customer to ensure layout meets foundry requirements  Experience: 3 + years Job Location: Bengaluru. Immediate/15 days preferred. Interested candidates, please share the updated resume:- av@sivalleytech.com

Custom Layout Engineer | Cyient Limited | Hyderabad & Bangalore

Job Code              :      JR-001963

Experience          :       4-12 years

Location                :      Hyderabad and Bangalore

Celebrating its twenty-fifth anniversary in 2016, Cyient is an acknowledged leader in engineering design services, design-led manufacturing, networks and operations, data transformation, and analytics. We collaborate with our clients to help them achieve more and together shape a better future. We call it Designing Tomorrow Together.

Our industry focus includes aerospace, defense, rail transportation, off-highway & industrial, power generation, mining, oil & gas, communications, utilities, geospatial, semiconductor and medical technology. We align closely with the business needs, goals, culture, and core values of our clients. This reflects in the deep, long-standing relationships we have developed and sustained with some of the leading names in these industries.

JOB DESCRIPTION SUMMARY

Job Role:

• Will be working on Custom Layout Analog IPs like PLL, ADCs, DACs, Voltage Reference Generators, High Speed IO's, and custom layout of Standard Cells.
• Performing verification checks like DRC/LVS/Antenna and fixing violations
• Work closely with the design engineers and layout engineers in designing and successfully delivering analog layouts.
• Need to work and review layouts which produce good yield.

Skills required: 

• Hands on Experience in Full Chip Layout (Other mixed signal or RF Layout would be plus)
• Experience Using Cadence Virtuoso Layout Editor, Mentor Graphics Calliber, Verification Tool (Assura or Hercules is plus).
• Performing various kinds of analog layouts, implementations from top-level, floor planning down to complex block level layouts
• Knowledge of various analog layout techniques, understanding of various circuit principles as affected by layout such as speed, capacitance, power, noise and area.
• Should have worked on Analog IC Layout, DRC/LVS/Antenna/LPE Checks, CMOS/BiCMOS Device Physics, CMOS/BiCMOS Fabrication Knowledge
• Perl and Shell Scripting (Preferred)

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