Exciting JOB Opportunities For Design & Verification Engineers in Synapse Design @ Bangalore

JOB LOCATION: -- BANGALORE

JOB DESCRIPTIONS: --

1.) Design Verification:-- IP or SoC (UVM based)
Experience :- 3 to 10 Years
UVM and System Verilog is must. 
Must have developed UVM based environment from scratch. 
Shall have worked on SoC level verification or IP level Verification. 
Knowledge of protocols such as AXI, AHP, I2C, SPI, DDR etc.

2.) Design Verification:-- 'C' based test cases
Experience :- 3 to 10 Years
Shall have worked on full chip level SoC verification with real processor. 
Test cases are in C and environment is either UVM/ System Verilog / Verilog.
Training center or bench projects will not be considered. 

3.) Design Verification:-- PCIe/Ethernet>1G/ USB3.0
Experience :- 4 to 10 Years
UVM and System Verilog is must. 
Must have developed UVM based environment from scratch. 
Shall have worked on PHY verification of PCIe Gen-2 or Gen-3. Ethernet 1G/10G/40G/100G and USB 3.0 can also be considered.

4.) Design Verification: -- ARM CPU
Experience: - 5 to 7 Years
Familiar with ARM CPU architecture.
Must be familiar with AMBA protocols (ACE, AXI, AHB, APB).
Strong in assembly C, system Verilog, UVM back ground.
Ability to trace, debug and root cause failures in the RTL code.
o Must be familiar with waveform debug using tools like Verdi.
o Motivated to do deep dive debug, using waveforms and logs.
Familiar with Gate Level simulations.
o Hands on experience with gate level simulations with and without timing.
Hands-on with post-silicon debug is preferable.

5.) Design:-- RTL
Experience : - 3 to 10 Years
Relevant SoC integration OR IP design experience. 
Experience for developing Micro architecture from specifications and take it up to RTL coding and synthesis. 
Experience on ARM processor based SoC Integration design will be advantage.

6.) AMS Verification
Experience: - 3 to 10 Years
Experience on 14nm/10nm/7nm much.(preferably TSMC).
Should have worked on blocks like PLL, LDO, VCO, Opamps etc.. Pcie / Serdes blocks.
Expertise with Cadence virtuoso XL for editing and Mentor graphics caliber for Verification.
Senior Engineer should have experience in IP integration.

7.) Design: -- FPGA

Experience: - 5 to 10 Years

Should have Digital design experience with FPGA background.
Strong digital design fundamentals.
Knowledge of Industry Standard Interfaces (SPI, I2C, etc) is preferable.
Experience in porting processor based designs to FPGA is a plus.
Designing digital blocks in Mixed Signal chip.
FPGA Validation of digital design (RTL + Firmware).
Experience with Xilinx Zync board is plus. 
Knowledge of modelling the peripheral / drivers / models to make the complete System setup for testing the SoC on FPGA.

Email Id : amithotkar@synapse-da.com