Opening for Memory Design position #Bangalore

Location : Bangalore Exp : 4-10 Years Required Skills: 1.Drawing layouts for schematics created by Design Engineers in 7nm & other FinFET technologies 2.Experience on Memory Layout. Like RAM, ROM, SDRAM etc. 3.Good knowledge on Memory layout techniques like Area/Speed/Power optimization 4.Good knowledge on different Memory Architecture & Compilers 5.Knowledge on BIT cell, data line & Address line routing concepts 6.Effectively communicate with Design Engineers to clarify and interpret the layout requirements based on the schematics 7.Prepare layout floor-plan & review it with the Design Engineer 8.Create layouts in the Cadence Virtuoso CAD platform as per floor-plan 9.Run DRC, LVS & other verifications required by customer to ensure layout meets foundry requirements 10.Provide feedback to Design Engineers on any modifications to schematics after layouts are completed 11.Support RC-extraction, IR drop & other post-layout analysis of layouts as per Design Engineers requirements Forward CV : sailaja.b@anantha.co.in For More Details Contact : 040 30021207 References will be appreciable