Experience : 4-12 years
Location : Hyderabad and Bangalore
Celebrating its twenty-fifth anniversary in 2016, Cyient is an acknowledged leader in engineering design services, design-led manufacturing, networks and operations, data transformation, and analytics. We collaborate with our clients to help them achieve more and together shape a better future. We call it Designing Tomorrow Together.
Our industry focus includes aerospace, defense, rail transportation, off-highway & industrial, power generation, mining, oil & gas, communications, utilities, geospatial, semiconductor and medical technology. We align closely with the business needs, goals, culture, and core values of our clients. This reflects in the deep, long-standing relationships we have developed and sustained with some of the leading names in these industries.
JOB DESCRIPTION SUMMARY
Job Role:
- Will be working on Custom Layout Analog IPs like PLL, ADCs, DACs, Voltage Reference Generators, High Speed IO's, and custom layout of Standard Cells.
- Performing verification checks like DRC/LVS/Antenna and fixing violations
- Work closely with the design engineers and layout engineers in designing and successfully delivering analog layouts.
- Need to work and review layouts which produce good yield.
Skills required:
- Hands on Experience in Full Chip Layout (Other mixed signal or RF Layout would be plus)
- Experience Using Cadence Virtuoso Layout Editor, Mentor Graphics Calliber, Verification Tool (Assura or Hercules is plus).
- Performing various kinds of analog layouts, implementations from top-level, floor planning down to complex block level layouts
- Knowledge of various analog layout techniques, understanding of various circuit principles as affected by layout such as speed, capacitance, power, noise and area.
- Should have worked on Analog IC Layout, DRC/LVS/Antenna/LPE Checks, CMOS/BiCMOS Device Physics, CMOS/BiCMOS Fabrication Knowledge
- Perl and Shell Scripting (Preferred)
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