We are urgently looking for Design Verification Engineer for our company.
Exp Level: 2-10 Yrs
NP: Immediate to 30 Days
Skills:-
Verilog, SystemVerilog, UVM/OVM
Job Description
o Working experience with standard protocols such as USB, PCIe, Ethernet, MIPI, AMBA Bus, etc.
o Must have experience with IP level and SoC level verification with test plan development, test bench coding
o Must have strong background in logic verification with very good debugging skill
o Experience in directed test and constrained randomized test development
o Must have experience in code coverage and functional coverage analysis
o Expertise in C, Verilog, SystemVerilog, UVM/OVM
o Gate Level Simulation will be a plus
Interested, please share your updated cv at supriya@digicomm.org
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