We are looking for IP VERIFICATION (#VLSI) ENGINEERS with 2+ years of experience. #Tessolve #Noida #Bangalore #Hyderabad #VLSI

We are looking for IP VERIFICATION (VLSI) ENGINEERS with 2+ years of experience. Location: Noida/Bangalore/Hyderabad JD: Key Technical Skills Self-starter with 2-12 years relevant experience on IP / Sub-system verification on multimillion Gate and complex Design with multiple clocks with minimal supervision Hands on knowledge with strong fundamentals of SV/ UVM (and Verilog) and ability to modify or develop checkers, monitors etc. from scratch. (Must have) Desirable exposure to formal verification, assertions/SVA, functional coverage and regression management. Ability to debug Testbench and RTL issues and handle legacy Testbench and make enhancements. Highly desirable experience in IP with system interface protocols like AMBA /AHB or AXI. Must have experience in end to end IP verification project cycle, including Testbench Strategies, TB development, simulation debugs. Experience desirable on at least one of the following: VCS (Synopsys), Incisive IES/IUS/Xcelium (Cadence) VC Formal (Synopsys), Jasper (Cadence) eManager / vManager (Cadence) or any other Regression Management Tool. Basic understanding of any Version Management and Ticketing tools. Interested can share their CV to heena.mahajan@tessolve.com