Interested can share CV to krishnaprasath.s@testandverification.com
JD is given below: Title: Verification Engineer Experience : 3+ years Location: Bangalore/Hyderabad/Chennai/Noida Notice period: Immediate to 45 days JD: Skill set Must Have · Block and Top level verification know-how · Verification Plan Development · System Verilog/OVM or UVM · Testbench Development · VHDL/Verilog simulation and debug · Scripting Nice to have · HVL: Systemverilog/Specman is a plus · End to End RTL Functional Verification Concepts · Understanding of power aware architecture
JD is given below: Title: Verification Engineer Experience : 3+ years Location: Bangalore/Hyderabad/Chennai/Noida Notice period: Immediate to 45 days JD: Skill set Must Have · Block and Top level verification know-how · Verification Plan Development · System Verilog/OVM or UVM · Testbench Development · VHDL/Verilog simulation and debug · Scripting Nice to have · HVL: Systemverilog/Specman is a plus · End to End RTL Functional Verification Concepts · Understanding of power aware architecture
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