Reach me with updated resume to Srinivasx.k.r@intel.com
No of positions :8 (Junior to senior level all are Individual Contributor Roles)
1.Soc Presilicon Verification-OVM/UVM,Verilog,IP Verification/PCIE/USB/Subsytem level
Experience-Masters 5-15Yrs Bachelors 7 -17 Yrs Individual Contributor Role
2.Physical Design Engineer: 8-15Yrs Senior Role Individual Contributor Technical Role.
Please do refer your friends for above skillset only
Freshers -Do not approach.Apply on Career Site Only
No of positions :8 (Junior to senior level all are Individual Contributor Roles)
1.Soc Presilicon Verification-OVM/UVM,Verilog,IP Verification/PCIE/USB/Subsytem level
Experience-Masters 5-15Yrs Bachelors 7 -17 Yrs Individual Contributor Role
2.Physical Design Engineer: 8-15Yrs Senior Role Individual Contributor Technical Role.
Please do refer your friends for above skillset only
Freshers -Do not approach.Apply on Career Site Only
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