Memory Layout Engineer
Good Understanding of memory compiler architectures, Tiling Methodology, Hands on Experience in Memory leaf cell layout development and involved in block and top level integrations, Well Versed with Design Rules for 40nm and below. Should have Completed Physical Verification at Block and Instance Level. EM/IR Closure at Instance Level is Plus. Proficiency with Custom IC Tools viz. Cadence Virtuoso, Cadence PVS, Calibre etc. is required.
The Candidate Must Possess Good Debugging and Interpersonal Skills
Please send profiles to career@yoctozant.com
Good Understanding of memory compiler architectures, Tiling Methodology, Hands on Experience in Memory leaf cell layout development and involved in block and top level integrations, Well Versed with Design Rules for 40nm and below. Should have Completed Physical Verification at Block and Instance Level. EM/IR Closure at Instance Level is Plus. Proficiency with Custom IC Tools viz. Cadence Virtuoso, Cadence PVS, Calibre etc. is required.
The Candidate Must Possess Good Debugging and Interpersonal Skills
Please send profiles to career@yoctozant.com
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