Tuesday, 27 March 2018

Walk In Drive for VLSI Engineers in all the major cities-

Chennai - April 6th and 7th. Bangalore - April 7th and 21st Ahmedabad - April 13th and 14th. Pune - April 20th and 21st. Roles -  IP Verification, PD, Analog Layout Min Experiece - 1.5years. Job Location - Bangalore. Roles - RTL Desig, ASIC Verification Min Experiece - 2.5years. Job Location - Bangalore. Role- Memory Layout Experience - 3-7 years Job Location - Taiwan For Registration mail your resume to prachi@chipsolcosultant.com

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