We are urgently looking for RTL Design Engineer (Exp: 2 -4 Years) for Chennai location.

•             Strong knowledge of RTL Design in Verilog,

•             Hands on experience in Linting & Synthesis tools - Understanding of Timing concepts

•             Hands on experience in Multi clock design & low power concepts

•             Strong Protocol Knowledge on AXI/AHB Bus and I2C

If you have the required skills, please share your profile to vipin@incise.in