#Tessolve is hiring RTL Design Engineers for #Bangalore location.

Tessolve is hiring RTL Design Engineers for Bangalore location. Interested with 3-5 years' relevant experience can share CV to heena.mahajan@tessolve.com Mandatory skills: Experience in Logic design / micro-architecture / RTL coding is a must. Expertise in Verilog/VHDL is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB. Experience in Synthesis / Understanding of timing concepts for ASIC Experience in design of DDR / USB / PCIe controller or such complex protocols is a plus. Hands on experience in Multi Clock designs, Asynchronous interface is a must.