Tessolve Semiconductor (A Hero Electronix venture) is hiring for RTL Design Engineer.

Interested can share CV to
Krishnaprasath.shanmugavel@tessolve.com JD is given below: Title: RTL Design Engineer Experience : 3+ years Location: Bangalore/Hyderabad Notice period: Immediate to 45 days JD: Responsible for IP / sub-system level micro-architecture development and RTL coding. - Prepare block/sub-system level timing constraints. - Integrate IP/sub-system. - Perform basic verification either in IP Verification environment - Experience in Logic design / micro-architecture / RTL coding is a must. - Expertise in Verilog/VHDL is a must. - Should have knowledge of AMBA protocols - AXI, AHB, APB. - Experience in Synthesis / Understanding of timing concepts for ASIC - Experience in design of DDR / USB / PCIe controller or such complex protocols is a plus. - Hands on experience in Multi Clock designs, Asynchronous interface is a must. - Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required. - Knowledge of low power concepts and experience is a plus.