Blueberry Hiring Signal Integrity/Power Integrity Engineer

Experience - 4 + Years Location - Bangalore JD: The project is an ASIC validation board. It includes the following interfaces : o Host interface Gen 3 PCIe at 8GB/s o DDR4 at 1600 and 2 Rank o Chip to Chip interface o Flash Interface The scope would include:  Host Interface  Chip to Chip  DDR  Flash o SI check for o Flash interface. Need to provide rules and guidance to layout to achieve the expected TM data rate and verify SI quality once the layout is completed o Host interface SI. o DDR interface SI. Expected outcome: o Simulation reports o Extracted board s-parameters models Interested please reach us natasha@blueberrysemi.com