Tuesday, 21 August 2018

Test and Verification Solutions Hiring Verification Engineers

Test and Verification Solutions Hiring Verification Engineers Skillset Block and Top level verification know-how Verification Plan Development System Verilog/OVM or UVM Testbench Development VHDL/Verilog simulation and debug Scripting Nice to have HVL: SystemVerilog/Specman is a plus Experience Must have 3+ Years Performing feature extraction from a specification Coverage closure Experience with other HVLs (e.g. System Verilog) and methodologies (e.g. UVM) Domain knowledge in DDR4/DDR3/LPDDR3 Location: Bangalore, Hyderabad,Chennai & Noida CTC: Best In the Industry Interested Candidates, Please Share Resumes with muralikrishna.g@testandverification.com

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