We have urgent openings with one of our product clients for Bangalore Location for following Skills:

RTL Design(ASIC/FPGA)- Minimum 3 years Verification(ASIC/SOC/IP/Functional)- 3+Years DFT- 3+Years Physical Design- 5+years Physical Design- Pune location- 1-3Years Analog layout- 4-12Years Analog Design- 8-15Years Interested Please Do share Updated CV at mounika.r@hiringninja.in Job Description can be shared on interest!!! Thanks & Regards, Mounika.