Hiring VLSI CAD Engineers for a Leading Product Company, Bangalore.

Exp: 4- 12 Years Notice Period: 1 month or less. Good experience in Logic Design flow,Verilog, Logic Synthesis Flow, DFT, RTL Linting, Formal Verification, Multi-Voltage Low Power Verification, CDC Verification. Good experience of Low-power design methodology flow, UPF/CPF etc Experience in Scripting like: TCL, Perl, Ruby, Shell, etc Experience in design methodology automation. Share CV to director@chipsolconsultant.com