Hiring now for RTL Design Engineer #Bangalore

Location : Bangalore Description: • Work with multiple SOC Design teams to rollout robust Synthesis, UPF QoR optimization and Timing Signoff flows • Provide implementation flows support and issue debugging services to SOC design teams across various site • Proficient in Perl/Python/Tcl, VLSI front end design steps- Verilog/VHDL, Synthesis. Interested, Please send me your resume at chandru@agnyasolutions.com Cheers! Chandru | 099946 99940