Sunday, 1 April 2018

Hiring 2016 and 2017 freshers for Design & Verification position

Hiring 2016 and 2017 freshers for Design & Verification position. Looking for candidates who have 70% and above percentage and also trained/done internship in System Verilog, UVM. Interviews will be conducted in April-2018. Interested candidates can drop me your resumes to madhav.motakadi@firstpass-semi.com

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