Looking for young Engineers for Intern positions at Synopsys,Bengaluru with below detials=>

New College graduates, B.E/B.Tech/M.E/M.Tech in Electronics or VLSI background. 1) Should have very good digital logic design knowledge. 2) Knowledge in Verilog/VHDL/FPGA design flow is required. 3) Good communication and inter-personal skills. 4) Exposure to Synplify or any FPGA synthesis software is a plus. Please send your resume to sarasrl@synopsys.com