#LeadSoc is #hiring for #DFT #Bangalore

JD: • Team Lead exposure and taking ownership of design deliverance • Primary responsibilities will include driving the DFT implementation and verification. • Define SCAN, MBIST, LBIST, JTAG architecture to meet highly aggressive test targets. • Coding DFT RTL and validating through formal verification. • Hands on execution on scan insertion, ATPG bringup and coverage analysis. • Define and support TEST mode STA constraints. • MBIST implementation and verification. • Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at. • Transition fault (TDF). • Path Delay fault (PDF). • Work closely with design team on IDDQ constrains validation. • Simulating and verifying the ATPG (SAF, TDF) and MBIST patterns on unit delay and timing corners. • SI debug and issue resolution DFT Tool expertise • ET (Encounter Test) • Fastscan • Test Kompress • Tessent • Simvision • TetraMax • DFTMax, • DFTAdvisor • DFTCompiler Interested Candidates kindly share updated Resume to #mahi@leadsoc.com